Automated UVM Tuning Orchestrated Via AI Reasoning
Abdul_Rehman
Verification in hardware design is a time-consuming and complex task as well as requires manual effort to update UVM testbench components...
Integrating TCAM IP into Chipyard via MMIO and RoCC Interfaces
Atharva Nerkar
This project focuses on integrating a Ternary Content Addressable Memory (TCAM) module into the Chipyard SoC framework to enable high-speed parallel...
AEGIS - AI-Enhanced Generation of Intelligent Scenarios
Mahnoor_Ismail
AEGIS automates hardware verification by using AI to generate optimized test cases. Parses Specifications: Extracts key features (interfaces,...
Running Secure and Vectorized Applications on SoC-Now
Muhammad Hussain_017
This project aims to develop and benchmark high-performance applications that leverage the modular SoC-Now platform, which integrates RISC-V cores, a...
PyUVM-Based General Testbench for RISC-V Cores
Nitin Grandhi
With the increasing adoption of RISC-V as an open-source Instruction Set Architecture (ISA), there is a growing need for effective and reusable...
